Design-Linked Incentive scheme

About Design-Linked Incentive scheme:

• It aims to offer financial incentives as well as design infrastructure support across various stages of development and deployment of semiconductor design(s) for Integrated Circuits (ICs), Chipsets, System on Chips (SoCs), Systems & IP Cores and semiconductor linked design(s) over a period of 5 years.
• Objectives
  • Nurturing and facilitating the growth of domestic companies, startups and MSMEs.
  • Achieving significant indigenization in semiconductor content and IPs involved in the electronic products deployed in the country, thereby facilitating import substitution and value addition in the electronics sector.
  • Strengthening and facilitating access to semiconductor design infrastructure for the startups and MSMEs.
• Duration: The scheme shall initially be for three (3) years from 01-01-2022.
• The scheme has three components
  • Chip Design infrastructure support: Under this C-DAC will set up the India Chip Centre to host the state-of-the-art design infrastructure (viz. EDA Tools, IP Cores and support for MPW (Multi Project Wafer fabrication) & post-silicon validation) and facilitate its access to supported companies.
  • Product Design Linked Incentive: Under this component, a reimbursement of up to 50% of the eligible expenditure subject to a ceiling of 15 Crore rupees per application will be provided as fiscal support to the approved applicants who are engaged in semiconductor design.
  • Deployment Linked Incentive: Under this an incentive of 6% to 4% of net sales turnover over 5 years subject to a ceiling of ₹30 Crore per application will be provided to approved applicants whose semiconductor design for Integrated Circuits (ICs), Chipsets, System on Chips (SoCs), Systems & IP Cores and semiconductor linked design are deployed in electronic products.
• Nodal Agency: C-DAC (Centre for Development of Advanced Computing)